Schematics 2.2 are finalized.

I will add no new features to it. Compared to the 2.1 implementation, it will add:

  • a jumper based USB/RS232 multiplexer.
  • interrupt driven serial communications. Both HW and SW flow control will be supported.
  • a simplified (and fixed) JK flip-flop based CPU clock generator with possible support for clock stretching via signals provided over an extension connector.
  • a divide by three circuit in the ACIA clock generation path. Serial communications will be either at 38400 or 115200 bps.
  • simplified CompactFlash connectivity over an inexpensive ATA/CF adapter.

All I need to do now is to thoroughly verify the thing, come up with a realistic and detailed enough bill of material and send the outcome to Jean-Marc for an initial PCB batch. I am still missing components (IC sockets, resistor networks, straps, headers and capacitors) that will eventually be needed for the first PCB trials. Stay tuned!


 

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